1. Field of the Invention
The present invention relates to a mixed-mode process, and more particularly, to a double poly mixed-mode process for forming a mixed-signal circuit embedded with a high resistance (HR) resistor.
2. Description of the Prior Art
In a semiconductor process, polysilicon is often positioned to function as resistors capable of providing various resistance values. High resistance resistors, which are widely used in the SRAM, analog, digital/analog mixed-mode, and radio frequency circuit designs, attract many major manufacturers to devote themselves in developing. When load transistors of a static random access memory (SRAM) is replaced by polysilicon resistors, the number of transistors in the SRAM can be reduced and thus saves cost and enhance the integration of the SRAM. Only when the polysilicon resistor is capable of providing a uniform and stable value of high resistance, the requirements for various circuit designs can be satisfied and to be carried out.
Please refer to FIG. 1 to FIG. 7. FIG. 1 to FIG. 7 are schematic diagrams illustrating a mixed-mode process according to the prior art method. As shown in FIG. 1, a semiconductor substrate 10 is provided first. The semiconductor substrate 10 has a surface comprising at least a first conductive region 12, at least a second conductive region 14, at least a metal-oxide-semiconductor (MOS) transistor region 16, and at least a capacitor region 18. Either portions of the surface of the semiconductor substrate 10 within the first conductive region 12, the second conductive region 14, or the capacitor region 18 further comprises a field oxide layer 22.
As shown in FIG. 2, a gate oxide layer 24 and a first polysilicon layer 26 are sequentially formed on the semiconductor substrate 10. The gate oxide layer 24 is formed by performing a thermal oxidation process, and the first polysilicon layer 26 is a doped polysilicon layer or an undoped polysilicon layer followed by an implantation process. In addition, a silicide layer (not shown) is optionally formed on the first polysilicon layer 26. The silicide layer (not shown), composed of tungsten silicide (WSix, where x=2.2˜2.3), is formed by performing a sputtering process and a rapid thermal process (RTP). For simplicity of description, steps employed to form the silicide layer (not shown) are neglected. The silicide layer (not shown) is also regarded as a polycide layer because there is come reaction between the first polysilicon layer 26 and the silicide layer (not shown).
As shown in FIG. 3, a first photo-etching-process (PEP) is performed to remove portions of the silicide layer (not shown) and the first polysilicon layer 26 to simultaneously form a bottom electrode plate 32 of a capacitor (not shown) and a gate 34 of a MOS transistor (not shown) respectively within the capacitor region 18 and the MOS transistor region 16. After that, an interpolysilicon oxide (IPO) layer 36 and a second polysilicon layer 38 are sequentially formed on the semiconductor substrate 10 to cover the bottom electrode plate 32 of the capacitor (not shown) and the gate 34 of the MOS transistor (not shown). The second polysilicon layer 38 may be formed by a deposition process followed by an ion implantation process, or be formed by an in-situ doped chemical vapor deposition (CVD) process. The dopants utilized in the ion implantation process may be N-type dopants, such as arsenic or phosphorus, or P-type dopants, such as boron. When the dopants are N-type, the dosage of the ion implantation process is approximately 1014˜16 atoms/cm2. When the dopants are P-type, the dosage of the ion implantation process is approximately 1012˜14 atoms/cm2. If the second polysilicon layer 38 is formed by an in-situ doped chemical vapor deposition process, a mixing gas containing phosphine (PH3) or arsine (AsH3) or diborane (B2H6), silane (SiH4), and nitrogen (N2) is added into the reaction chamber to form the doped second polysilicon layer 38 in one step to achieve the equivalent result. Therefore, the second polysilicon layer 38 is doped with N-type dopants or P-type dopants.
As shown in FIG. 4, a second PEP is performed to remove portions of the second polysilicon layer 38 by utilizing the IPO layer 36 as a stop layer, to simultaneously form a first conductive wire 42, a second conductive wire 44, and a top electrode plate 46 of the capacitor (not shown) respectively within the first conductive region 12, the second conductive region 14, and the capacitor region 18. The IPO layer 36 not between the bottom electrode plate 32 and the top electrode plate 46, not below the first conductive wire 42 and the second conductive wire 44 is thereafter removed by a wet dip process, and the IPO layer 36 between the bottom electrode plate 32 and the top electrode plate 46 is employed as a capacitor dielectric layer 48 of the capacitor 52, as shown in FIG. 5. The conductive wires 42, 44 are optionally employed as resistors of the integration circuits depending on the layout of the integration circuits.
A dielectric layer (not shown), composed of tetra-ethyloxysilane (TEOS), is formed on the semiconductor substrate 10 to cover the first conductive wire 42, the second conductive wire 44, the gate 34, and the capacitor 52. By using surfaces of the field oxide layers 22 and the gate oxide layer 24 as a stop layer, a first etching process is performed to remove portions of the dielectric layer (not shown) to form a spacer 54 on either sides of the first conductive wire 42, a spacer 56 on either sides of the second conductive wire 44, a spacer 58 on either sides of the gate 34 of the MOS transistor (not shown), a spacer 62 on one side of the capacitor 52, and spacers 64, 66 on another side of the capacitor 52. It is worth noting that the spacers 64, 66 at one side of the capacitor 52 has a different shape from the other spacers 54, 56, 58, 62 owing to the unequal widths of the bottom electrode plate 32 and the top electrode plate 46 of the capacitor 52. In addition, an ion implantation process may be performed to form a lightly doped drain (LDD, not shown) in portions of the semiconductor substrate 10 adjacent to either sides of the gate 34 before the spacers 54, 56, 58, 62, 64, 66 are formed.
As shown in FIG. 6, a high resistance (HR) mask 72 is then formed on the semiconductor substrate 10. The HR mask 72 covers the capacitor 52, the first conductive wire 42, the gate 34 of the MOS transistor (not shown), and exposes the second conductive wire 44. After that, a first ion implantation process is performed to dope the second conductive wire 44 with dopants having an opposite type to the dopants used in doping the second polysilicon layer 38. That means, the second conductive wire 44 is doped with P-type dopants, such as boron, or N-type dopants, such as arsenic or phosphorus, when the dopants used in doping the second polysilicon layer 38 are N-type or P-type, respectively. The first ion implantation process is thus called a high resistance implantation process. When the dopants are P-type, the dosage of the first ion implantation process is approximately 1013˜15 atoms/cm2. When the dopants are N-type, the dosage of the first ion implantation process is approximately 1013 ˜15 atoms/cm2. No matter what type of dopant is utilized to dope the second polysilicon layer 38, the resultant dopant concentration is high. It is obvious that the dopant concentration achieved by the first ion implantation process is lower than the dopant concentration in the second polysilicon layer 38. Therefore, some of the dopants which already exist in the second conductive wire 44 are neutralized by the opposite type dopants doped by the first ion implantation process, and the not neutralized dopants in the second conductive wire 44 directly contribute to the resistance of the second conductive wire 46 to form a high resistance resistor. In contrast with the second conductive wire 44, the first conductive wire 42 which is not doped with opposite dopants is a low resistance resistor.
As shown in FIG. 7, the HR mask 72 is removed. After that, a source 74 and a drain 76 of the MOS transistor 78 are formed in portions of the semiconductor substrate 10 adjacent to but not contiguous to either sides of the gate 34, by performing a second implantation process, to complete the fabricating of the MOS transistor 78.
However, the dosage and/or implant energy of the high resistance implantation process reach a saturation status. That means, the resistance value of the high resistance resistor formed according to the prior art mixed-mode process can only reach to the order of thousands order since the neutralization ability of the high resistance implantation process is limited. In the modern electrical industry, such a resistance value is not high enough so that resistors having such a resistance value cannot fulfill the requirements for modern circuit designs. Moreover, the high dosage and/or implant energy of the high resistance implantation process tend to cause processing problems. Therefore, it is very important to develop a mixed-mode process to form the polysilicon resistor having a uniform and stable value of high resistance. At the same time, the new developed mixed-mode process should not add complexity to processing and cost to products due to any extra photolithography steps.